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20UPGFC0084923 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6573969c35689ddfe79d02da

This Revision: 6573969c35689ddfe79d02db

Latest Revision: 6573969c35689ddfe79d02db

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	5

Parameter

ADCcalPar	9.453 0.18 10000.0
Name	0x14bbb
ChipId	15
InjCap	7.809
NfDSLDO	1.2865812960929401
NfASLDO	1.2851934599918198
NfACB	1.295409078303157
VcalPar	3.116 0.193
IrefTrim	7
KSenseInA	21087.503
KSenseInD	21387.785

KSenseShuntA	26108.337047619047
KSenseShuntD	26480.114761904762
KShuntA	1065.937
KShuntD	1040.952

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	10
SldoTrimD	5

Parameter

ADCcalPar	9.453 0.18 10000.0
Name	0x14bbb
ChipId	15
InjCap	7.809
NfDSLDO	1.2865812960929401
NfASLDO	1.2851934599918198
NfACB	1.295409078303157
VcalPar	3.116 0.193
IrefTrim	7
KSenseInA	21087.503
KSenseInD	21387.785
KSenseShuntA	26108.337047619047
KSenseShuntD	26480.114761904762
KShuntA	1065.937
KShuntD	1040.952