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20UPGFC0084900 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6573969c35689ddfe79d02d8

This Revision: 6573969c35689ddfe79d02d9

Latest Revision: 6573969c35689ddfe79d02d9

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	7.467 0.186 10000.0
Name	0x14ba4
ChipId	14
InjCap	7.891
NfDSLDO	1.2874531246568417
NfASLDO	1.2862939274058112
NfACB	1.2846910867624108
VcalPar	4.146 0.198
IrefTrim	7
KSenseInA	21523.868
KSenseInD	21615.946

KSenseShuntA	26648.598476190477
KSenseShuntD	26762.59980952381
KShuntA	1087.728
KShuntD	1080.845

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	7

Parameter

ADCcalPar	7.467 0.186 10000.0
Name	0x14ba4
ChipId	14
InjCap	7.891
NfDSLDO	1.2874531246568417
NfASLDO	1.2862939274058112
NfACB	1.2846910867624108
VcalPar	4.146 0.198
IrefTrim	7
KSenseInA	21523.868
KSenseInD	21615.946
KSenseShuntA	26648.598476190477
KSenseShuntD	26762.59980952381
KShuntA	1087.728
KShuntD	1080.845