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20UPGFC0084898 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6573969c35689ddfe79d02d4

This Revision: 6573969c35689ddfe79d02d5

Latest Revision: 6573969c35689ddfe79d02d5

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	10
SldoTrimD	12

Parameter

ADCcalPar	8.53 0.183 10000.0
Name	0x14ba2
ChipId	12
InjCap	8.131
NfDSLDO	1.2917436126062292
NfASLDO	1.2911996663148646
NfACB	1.2889093661406978
VcalPar	4.226 0.197
IrefTrim	8
KSenseInA	21462.922
KSenseInD	21718.393

KSenseShuntA	26573.141523809525
KSenseShuntD	26889.43895238095
KShuntA	1095.511
KShuntD	1079.737

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	10
SldoTrimD	12

Parameter

ADCcalPar	8.53 0.183 10000.0
Name	0x14ba2
ChipId	12
InjCap	8.131
NfDSLDO	1.2917436126062292
NfASLDO	1.2911996663148646
NfACB	1.2889093661406978
VcalPar	4.226 0.197
IrefTrim	8
KSenseInA	21462.922
KSenseInD	21718.393
KSenseShuntA	26573.141523809525
KSenseShuntD	26889.43895238095
KShuntA	1095.511
KShuntD	1079.737