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20UPGFC0084902 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: cold

Config: 6573969c35689ddfe79d02ce

This Revision: 6573969c35689ddfe79d02cf

Latest Revision: 6573969c35689ddfe79d02cf

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	11
SldoTrimD	9

Parameter

ADCcalPar	13.844 0.193 10000.0
Name	0x14ba6
ChipId	13
InjCap	7.609
NfDSLDO	1.285562530508444
NfASLDO	1.2843755317762744
NfACB	1.2819300283642139
VcalPar	3.282 0.208
IrefTrim	7
KSenseInA	21295.125
KSenseInD	21759.103

KSenseShuntA	26365.39285714286
KSenseShuntD	26939.84180952381
KShuntA	1071.657
KShuntD	1069.236

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	11
SldoTrimD	9

Parameter

ADCcalPar	13.844 0.193 10000.0
Name	0x14ba6
ChipId	13
InjCap	7.609
NfDSLDO	1.285562530508444
NfASLDO	1.2843755317762744
NfACB	1.2819300283642139
VcalPar	3.282 0.208
IrefTrim	7
KSenseInA	21295.125
KSenseInD	21759.103
KSenseShuntA	26365.39285714286
KSenseShuntD	26939.84180952381
KShuntA	1071.657
KShuntD	1069.236