20UPGFC0084903 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 65736b5f35689ddfe79d0139

This Revision: 65736b5f35689ddfe79d013a

Latest Revision: 65736b5f35689ddfe79d013a

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0

DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	6

Parameter

ADCcalPar	13.3 0.198 10000.0
Name	0x14ba7
ChipId	15
InjCap	7.716
NfDSLDO	1.287711231913005
NfASLDO	1.286665639726566
NfACB	1.2847893030632294
VcalPar	4.367 0.212
IrefTrim	11
KSenseInA	20851.297
KSenseInD	21720.248

KSenseShuntA	25815.891523809525
KSenseShuntD	26891.73561904762
KShuntA	1072.052
KShuntD	1056.779

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	6

Parameter

ADCcalPar	13.3 0.198 10000.0
Name	0x14ba7
ChipId	15
InjCap	7.716
NfDSLDO	1.287711231913005
NfASLDO	1.286665639726566
NfACB	1.2847893030632294
VcalPar	4.367 0.212
IrefTrim	11
KSenseInA	20851.297
KSenseInD	21720.248
KSenseShuntA	25815.891523809525
KSenseShuntD	26891.73561904762
KShuntA	1072.052
KShuntD	1056.779