20UPGFC0084905 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 65736b5f35689ddfe79d0137

This Revision: 65736b5f35689ddfe79d0138

Latest Revision: 65736b5f35689ddfe79d0138

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	7.227 0.19 10000.0
Name	0x14ba9
ChipId	14
InjCap	7.73
NfDSLDO	1.2857871939892718
NfASLDO	1.2848572783552323
NfACB	1.2828257703547152
VcalPar	3.627 0.204
IrefTrim	9
KSenseInA	20814.391
KSenseInD	21500.465

KSenseShuntA	25770.19838095238
KSenseShuntD	26619.623333333333
KShuntA	1058.993
KShuntD	1082.248

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	10

Parameter

ADCcalPar	7.227 0.19 10000.0
Name	0x14ba9
ChipId	14
InjCap	7.73
NfDSLDO	1.2857871939892718
NfASLDO	1.2848572783552323
NfACB	1.2828257703547152
VcalPar	3.627 0.204
IrefTrim	9
KSenseInA	20814.391
KSenseInD	21500.465
KSenseShuntA	25770.19838095238
KSenseShuntD	26619.623333333333
KShuntA	1058.993
KShuntD	1082.248