20UPGFC0084904 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 65736b5f35689ddfe79d0133

This Revision: 65736b5f35689ddfe79d0134

Latest Revision: 65736b5f35689ddfe79d0134

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2

DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	6
SldoTrimD	9

Parameter

ADCcalPar	10.78 0.195 10000.0
Name	0x14ba8
ChipId	12
InjCap	7.8100000000000005
NfDSLDO	1.28708001110426
NfASLDO	1.2865933158134537
NfACB	1.2840882665225395
VcalPar	3.559 0.208
IrefTrim	15
KSenseInA	21067.071
KSenseInD	22245.396

KSenseShuntA	26083.040285714287
KSenseShuntD	27541.918857142857
KShuntA	1087.518
KShuntD	1080.234

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	6
SldoTrimD	9

Parameter

ADCcalPar	10.78 0.195 10000.0
Name	0x14ba8
ChipId	12
InjCap	7.8100000000000005
NfDSLDO	1.28708001110426
NfASLDO	1.2865933158134537
NfACB	1.2840882665225395
VcalPar	3.559 0.208
IrefTrim	15
KSenseInA	21067.071
KSenseInD	22245.396
KSenseShuntA	26083.040285714287
KSenseShuntD	27541.918857142857
KShuntA	1087.518
KShuntD	1080.234