20UPGFC0087242 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 655e58373edcf47cdd8936bb

This Revision: 657b51ad455ee9774c34f782

Latest Revision: 657b51ad455ee9774c34f782

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA6
SldoTrimD6

Parameter

ADCcalPar
  • 10.408
  • 0.192
  • 10000.0
Name0x154ca
ChipId15
InjCap7.939000000000001
NfDSLDO1.289132963887313
NfASLDO1.2879841832034735
NfACB1.2860599755580426
VcalPar
  • 2.752
  • 0.206
IrefTrim15
KSenseInA20981.947
KSenseInD21628.246
KSenseShuntA25977.648666666668
KSenseShuntD26777.828380952382
KShuntA1062.6
KShuntD1015.279

PixelConfig

Diff from previous revision 657b4c70455ee9774c34f23d

No diff is present.