20UPGFC0087242 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: warm

Config: 655e582d3edcf47cdd8936b9

This Revision: 657b5992c6dc065e6e076052

Latest Revision: 657b5d5a5de20d9d66b48bda

Global Config

AiRegionRow0
AuroraActiveLanes1
AuroraCBSend0
AuroraCBWait04095
AuroraCBWait10
AuroraCCSend3
AuroraCCWait25
AuroraEnPrbs0
AuroraInitWait32
AutoRead0137
AutoRead1133
AutoRead2121
AutoRead3122
AutoRead4124
AutoRead5127
AutoRead6126
AutoRead7125
BcidCnt0
BitFlipErrCnt0
BitFlipWngCnt0
CapMeasEn0
CapMeasEnPar0
CdrClkSel0
CdrCp40
CdrCpBuff200
CdrCpFd400
CdrOverwriteLimit0
CdrPhaseDetSel0
CdrVco1023
CdrVcoBuff500
ChSyncLockThr31
CmdErrCnt0
CmlBias0800
CmlBias1400
CmlBias20
DataEnBcid0
DataEnBinaryRo0
DataEnEos1
DataEnHitRemoval0
DataEnIsoHitRemoval0
DataEnL1id0
DataEnRaw0
DataMaxHits0
DataMaxTot0
DataMergeEn0
DataMergeEnBond0
DataMergeEnClkGate0
DataMergeInMux00
DataMergeInMux11
DataMergeInMux22
DataMergeInMux33
DataMergeInPol0
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
DataMergeSelClk0
DataReadDelay0
DiffComp500
DiffFbCapEn0
DiffLcc100
DiffLccEn0
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffTh1L326
DiffTh1M257
DiffTh1R326
DiffTh250
DiffVff60
EfuseConfig3855
EfuseReadData00
EfuseReadData10
EfuseWriteData00
EfuseWriteData10
EnChipId0
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
EnCoreColCal00
EnCoreColCal10
EnCoreColCal20
EnCoreColCal30
ErrWngMask0
EvenMask0
FineDelayClk0
FineDelayData0
GcrDefaultConfig44149
GcrDefaultConfigB21386
GlobalPulseConf0
GlobalPulseWidth10
GpCmosDs0
GpCmosEn1
GpCmosRoute34
GpLvdsBias7
GpLvdsEn15
GpLvdsPad00
GpLvdsPad11
GpLvdsPad233
GpLvdsPad335
GpValReg5
HitOrCnt00
HitOrCnt10
HitOrCnt20
HitOrCnt30
HitOrMask00
HitOrMask10
HitOrMask20
HitOrMask30
InjAnaMode0
InjDigEn0
InjFineDelay5
InjVcalHigh818
InjVcalMed200
InjVcalRange1
Latency500
LinComp110
LinCompTa110
LinFc20
LinGdacL408
LinGdacM408
LinGdacR408
LinKrumCurr50
LinLdac100
LinPreampL300
LinPreampM300
LinPreampR300
LinPreampT300
LinPreampTL300
LinPreampTR300
LinRefKrum300
LockLossCnt0
MonAdcTrim0
MonSensAcbDem0
MonSensAcbEn0
MonSensAcbSelBias0
MonSensSldoAnaDem0
MonSensSldoAnaEn0
MonSensSldoAnaSelBias0
MonSensSldoDigDem0
MonSensSldoDigEn0
MonSensSldoDigSelBias0
MonitorEnable1
MonitorI63
MonitorV32
MonitoringDataAdc0
NtcDac100
NumOfEventsInStream1
OddMask0
PixAutoRow1
PixBroadcast0
PixConfMode1
PixDefaultConfig40162
PixDefaultConfigB25373
PixPortal5541
PixRegionCol199
PixRegionRow0
PtotCoreColEn00
PtotCoreColEn10
PtotCoreColEn20
PtotCoreColEn30
RdWrFifoErrCnt0
ReadTrigCnt0
ReadTrigLatency1000
RingOscAClear0
RingOscAEn0
RingOscAOut0
RingOscARoute0
RingOscBClear0
RingOscBEnBl0
RingOscBEnBr0
RingOscBEnCapA0
RingOscBEnFf0
RingOscBEnLvt0
RingOscBOut0
RingOscBRoute0
RstCoreCol00
RstCoreCol10
RstCoreCol20
RstCoreCol30
SelfTrigDelay512
SelfTrigDigThr1
SelfTrigDigThrEn0
SelfTrigEn0
SelfTrigMulti4
SelfTrigPattern65534
SerEnLane1
SerEnTap1
SerInvTap1
SerSelOut01
SerSelOut11
SerSelOut21
SerSelOut31
ServiceBlockEn1
ServiceBlockPeriod50
SkippedTrigCnt0
SldoEnUndershuntA0
SldoEnUndershuntD0
SldoTrimA6
SldoTrimD6
TotEn6b4b0
TotEn800
TotEnPtoa0
TotEnPtot0
TotPtotLatency500
TrigCnt0
TruncTimeoutConf0
TwoLevelTrig0
VrefIn1
VrefRsensBot0
VrefRsensTop0

Parameter

ADCcalPar
  • 9.0
  • 0.1940000057220459
  • 10000.0
ChipId15
EnforceNameIdCheckTrue
InjCap7.409999847412109
IrefTrim15
KSenseInA20981.947265625
KSenseInD21628.24609375
KSenseShuntA25977.6484375
KSenseShuntD26777.828125
KShuntA1062.5999755859375
KShuntD1015.2789916992188
Name0x154ca
NfACB1.2860599756240845
NfASLDO1.2879841327667236
NfDSLDO1.2891329526901245
NtcCalPar
  • 0.0007488999981433153
  • 0.0002769000129774213
  • 7.059500006789676e-08
VcalPar
  • -0.0
  • 0.20999999344348907

PixelConfig

Diff from previous revision 657b5976f675a2071096858f

No diff is present.