20UPGFC0087210 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: LP

Config: 655e58233edcf47cdd8936b1

This Revision: 657b51a2455ee9774c34f77d

Latest Revision: 657b51a2455ee9774c34f77d

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD6

Parameter

ADCcalPar
  • 10.252
  • 0.19
  • 10000.0
Name0x154aa
ChipId13
InjCap7.68
NfDSLDO1.2867066834973793
NfASLDO1.2855430750908627
NfACB1.2833307825648927
VcalPar
  • 6.383
  • 0.205
IrefTrim10
KSenseInA21323.965
KSenseInD21836.127
KSenseShuntA26401.099523809524
KSenseShuntD27035.204857142857
KShuntA1052.258
KShuntD1058.307

PixelConfig

Diff from previous revision 657b4c67455ee9774c34f22a

No diff is present.