20UPGFC0087210 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 655e58223edcf47cdd8936af

This Revision: 657b51a1455ee9774c34f77c

Latest Revision: 657b51a1455ee9774c34f77c

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD6

Parameter

ADCcalPar
  • 10.252
  • 0.19
  • 10000.0
Name0x154aa
ChipId13
InjCap7.68
NfDSLDO1.2867066834973793
NfASLDO1.2855430750908627
NfACB1.2833307825648927
VcalPar
  • 6.383
  • 0.205
IrefTrim10
KSenseInA21323.965
KSenseInD21836.127
KSenseShuntA26401.099523809524
KSenseShuntD27035.204857142857
KShuntA1052.258
KShuntD1058.307

PixelConfig

Diff from previous revision 657b4c67455ee9774c34f229

No diff is present.