20UPGFC0087194 Chip Configuration

Stage: MODULE/POST_PARYLENE_WARM

Branch: cold

Config: 655e58183edcf47cdd8936a9

This Revision: 657b4c62455ee9774c34f21f

Latest Revision: 657b519f455ee9774c34f779

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane4
SldoTrimA9
SldoTrimD8

Parameter

ADCcalPar
  • 6.603
  • 0.195
  • 10000.0
Name0x1549a
ChipId12
InjCap7.777
NfDSLDO1.2848766554438384
NfASLDO1.283598457016135
NfACB1.2816021695841033
VcalPar
  • 3.407
  • 0.208
IrefTrim10
KSenseInA21072.034
KSenseInD21756.235
KSenseShuntA26089.18495238095
KSenseShuntD26936.290952380954
KShuntA1067.238
KShuntD1068.089

PixelConfig

Diff from previous revision 655e5ad83edcf47cdd8936c2

No diff is present.