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20UPGFC0087194 Chip Configuration

Stage: MODULE/PARYLENE_MASKING

Branch: LP

Config: 655d2188502eb73330093af7

This Revision: 655d2189502eb73330093af8

Latest Revision: 655d2189502eb73330093af8

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0

DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	6.603 0.195 10000.0
Name	0x1549a
ChipId	12
InjCap	7.777
NfDSLDO	1.2848766554438384
NfASLDO	1.283598457016135
NfACB	1.2816021695841033
VcalPar	3.407 0.208
IrefTrim	10
KSenseInA	21072.034
KSenseInD	21756.235

KSenseShuntA	26089.18495238095
KSenseShuntD	26936.290952380954
KShuntA	1067.238
KShuntD	1068.089

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	6.603 0.195 10000.0
Name	0x1549a
ChipId	12
InjCap	7.777
NfDSLDO	1.2848766554438384
NfASLDO	1.283598457016135
NfACB	1.2816021695841033
VcalPar	3.407 0.208
IrefTrim	10
KSenseInA	21072.034
KSenseInD	21756.235
KSenseShuntA	26089.18495238095
KSenseShuntD	26936.290952380954
KShuntA	1067.238
KShuntD	1068.089