20UPGFC0087242 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 654288673faab532f97d135a

This Revision: 66903204986c92f58805d2cd

Latest Revision: 66f6cd3026024409f01973a0

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA6
SldoTrimD6

Parameter

ADCcalPar
  • 10.408
  • 0.192
  • 10000.0
Name0x154ca
ChipId15
InjCap7.939000000000001
NfDSLDO1.289132963887313
NfASLDO1.2879841832034735
NfACB1.2860599755580426
VcalPar
  • 2.752
  • 0.206
IrefTrim15
KSenseInA20981.947
KSenseInD21628.246
KSenseShuntA25977.648666666668
KSenseShuntD26777.828380952382
KShuntA1062.6
KShuntD1015.279

PixelConfig

Diff from previous revision 66901c3c637f6fcaf84df93f

No diff is present.