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20UPGFC0087226 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 654288673faab532f97d1358

This Revision: 66f45b8accf5a40aa86273c7

Latest Revision: 66f6cd2d26024409f0197397

Global Config

AuroraActiveLanes	1
CdrClkSel	0
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	32
ServiceBlockEn	1
ServiceBlockPeriod	50
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1

DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	8
SldoTrimD	5

Parameter

ADCcalPar	12.566 0.191 10000.0
Name	0x154ba
ChipId	14
InjCap	7.746
NfDSLDO	1.2865997914556448
NfASLDO	1.2847906316480049
NfACB	1.2829814718403645
VcalPar	4.835 0.204
IrefTrim	10
KSenseInA	21047.775
KSenseInD	21589.087

KSenseShuntA	26059.15
KSenseShuntD	26729.34580952381
KShuntA	1068.256
KShuntD	1033.795

PixelConfig

Diff from previous revision 6695c0361f90154eec9d9c97

No diff is present.