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20UPGFC0087242 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: warm

Config: 654288663faab532f97d134a

This Revision: 654288663faab532f97d134b

Latest Revision: 67180faf2f6ccc2b1c7b095d

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	6
SldoTrimD	6

Parameter

ADCcalPar	10.408 0.192 10000.0
Name	0x154ca
ChipId	15
InjCap	7.939000000000001
NfDSLDO	1.289132963887313
NfASLDO	1.2879841832034735
NfACB	1.2860599755580426
VcalPar	2.752 0.206
IrefTrim	15
KSenseInA	20981.947
KSenseInD	21628.246

KSenseShuntA	25977.648666666668
KSenseShuntD	26777.828380952382
KShuntA	1062.6
KShuntD	1015.279

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	6
SldoTrimD	6

Parameter

ADCcalPar	10.408 0.192 10000.0
Name	0x154ca
ChipId	15
InjCap	7.939000000000001
NfDSLDO	1.289132963887313
NfASLDO	1.2879841832034735
NfACB	1.2860599755580426
VcalPar	2.752 0.206
IrefTrim	15
KSenseInA	20981.947
KSenseInD	21628.246
KSenseShuntA	25977.648666666668
KSenseShuntD	26777.828380952382
KShuntA	1062.6
KShuntD	1015.279