20UPGFC0087210 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: warm

Config: 654288663faab532f97d1346

This Revision: 6695b2841f90154eec9d9b32

Latest Revision: 67180fa42f6ccc2b1c7b093f

Global Config

AuroraActiveLanes1
CdrClkSel0
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV32
ServiceBlockEn1
ServiceBlockPeriod50
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD6

Parameter

ADCcalPar
  • 8.0
  • 0.192
  • 10000.0
Name0x154aa
ChipId13
InjCap7.16
NfDSLDO1.2867066834973793
NfASLDO1.2855430750908627
NfACB1.2833307825648927
VcalPar
  • -2.0
  • 0.2
IrefTrim10
KSenseInA21323.965
KSenseInD21836.127
KSenseShuntA26401.099523809524
KSenseShuntD27035.204857142857
KShuntA1052.258
KShuntD1058.307

PixelConfig

Diff from previous revision 66955ae104560d1a00e397cf

RD53B
Parameter
ADCcalPar
$insert
    • 1
    • 0.192
$delete
  • 1