20UPGFC0090770 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 65395a913598ab59a30e3a66

This Revision: 65395a913598ab59a30e3a67

Latest Revision: 6539a9d23598ab59a30e3d74

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA4
SldoTrimD6

Parameter

ADCcalPar
  • 7.014
  • 0.197
  • 10000.0
Name0x16292
ChipId15
InjCap7.993
NfDSLDO-0.015637672243005996
NfASLDO-0.015637672243005996
NfACB-0.015637672243005996
VcalPar
  • 4.57
  • 0.211
IrefTrim14
KSenseInA20752.322
KSenseInD21121.703
KSenseShuntA25693.351047619046
KSenseShuntD26150.679904761906
KShuntA1100.504
KShuntD1046.533

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA4
SldoTrimD6
Parameter
ADCcalPar
  • 7.014
  • 0.197
  • 10000.0
Name0x16292
ChipId15
InjCap7.993
NfDSLDO-0.015637672243005996
NfASLDO-0.015637672243005996
NfACB-0.015637672243005996
VcalPar
  • 4.57
  • 0.211
IrefTrim14
KSenseInA20752.322
KSenseInD21121.703
KSenseShuntA25693.351047619046
KSenseShuntD26150.679904761906
KShuntA1100.504
KShuntD1046.533