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20UPGFC0090710 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 65395a903598ab59a30e3a62

This Revision: 65395a903598ab59a30e3a63

Latest Revision: 6539a9cd3598ab59a30e3d62

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	5

Parameter

ADCcalPar	13.779 0.195 10000.0
Name	0x16256
ChipId	13
InjCap	7.687
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	3.466 0.208
IrefTrim	15
KSenseInA	20764.518
KSenseInD	21204.975

KSenseShuntA	25708.450857142856
KSenseShuntD	26253.77857142857
KShuntA	1037.081
KShuntD	1017.363

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	8
SldoTrimD	5

Parameter

ADCcalPar	13.779 0.195 10000.0
Name	0x16256
ChipId	13
InjCap	7.687
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	3.466 0.208
IrefTrim	15
KSenseInA	20764.518
KSenseInD	21204.975
KSenseShuntA	25708.450857142856
KSenseShuntD	26253.77857142857
KShuntA	1037.081
KShuntD	1017.363