20UPGFC0087173 Chip Configuration

Stage: MODULE/INITIAL_COLD

Branch: LP

Config: 653045e0e34075ce6c46c99f

This Revision: 653045e0e34075ce6c46c9a0

Latest Revision: 653045e0e34075ce6c46c9a0

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD10

Parameter

ADCcalPar
  • 10.672
  • 0.189
  • 10000.0
Name0x15485
ChipId15
InjCap7.679
NfDSLDO1.2863116762719595
NfASLDO1.2849325154677993
NfACB1.2831080006539617
VcalPar
  • 2.974
  • 0.203
IrefTrim12
KSenseInA21215.082
KSenseInD21604.762
KSenseShuntA26266.292
KSenseShuntD26748.752952380954
KShuntA1069.783
KShuntD1057.365

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA10
SldoTrimD10
Parameter
ADCcalPar
  • 10.672
  • 0.189
  • 10000.0
Name0x15485
ChipId15
InjCap7.679
NfDSLDO1.2863116762719595
NfASLDO1.2849325154677993
NfACB1.2831080006539617
VcalPar
  • 2.974
  • 0.203
IrefTrim12
KSenseInA21215.082
KSenseInD21604.762
KSenseShuntA26266.292
KSenseShuntD26748.752952380954
KShuntA1069.783
KShuntD1057.365