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20UPGFC0078040 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 652ed687902554c217092f7f

This Revision: 652ed687902554c217092f80

Latest Revision: 658228e3df900555e744fa3b

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	14.732 0.193 10000.0
Name	0x130d8
ChipId	14
InjCap	8.144
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	3.666 0.206
IrefTrim	14
KSenseInA	20797.168
KSenseInD	21353.58

KSenseShuntA	25748.874666666667
KSenseShuntD	26437.765714285713
KShuntA	1050.974
KShuntD	1031.558

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	5
SldoTrimD	7

Parameter

ADCcalPar	14.732 0.193 10000.0
Name	0x130d8
ChipId	14
InjCap	8.144
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	3.666 0.206
IrefTrim	14
KSenseInA	20797.168
KSenseInD	21353.58
KSenseShuntA	25748.874666666667
KSenseShuntD	26437.765714285713
KShuntA	1050.974
KShuntD	1031.558