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20UPGFC0078012 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: cold

Config: 652ed686902554c217092f72

This Revision: 652ed686902554c217092f73

Latest Revision: 652ed686902554c217092f73

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0

DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	14.901 0.192 10000.0
Name	0x130bc
ChipId	12
InjCap	8.139
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	1.97 0.207
IrefTrim	12
KSenseInA	20967.602
KSenseInD	21129.558

KSenseShuntA	25959.88819047619
KSenseShuntD	26160.405142857144
KShuntA	1071.399
KShuntD	1034.13

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	2
DataMergeOutMux1	3
DataMergeOutMux2	0
DataMergeOutMux3	1
SerEnLane	4
SldoTrimA	9
SldoTrimD	8

Parameter

ADCcalPar	14.901 0.192 10000.0
Name	0x130bc
ChipId	12
InjCap	8.139
NfDSLDO	-0.015637672243005996
NfASLDO	-0.015637672243005996
NfACB	-0.015637672243005996
VcalPar	1.97 0.207
IrefTrim	12
KSenseInA	20967.602
KSenseInD	21129.558
KSenseShuntA	25959.88819047619
KSenseShuntD	26160.405142857144
KShuntA	1071.399
KShuntD	1034.13