20UPGFC0087178 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 64e51b62fc7088729756ae05

This Revision: 64e51b62fc7088729756ae06

Latest Revision: 64e51b62fc7088729756ae06

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA7
SldoTrimD9

Parameter

ADCcalPar
  • 11.602
  • 0.182
  • 10000.0
Name0x1548a
ChipId15
InjCap7.780000000000001
NfDSLDO1.2846440826516143
NfASLDO1.2841414776270468
NfACB1.2816571727913266
VcalPar
  • 3.201
  • 0.196
IrefTrim8
KSenseInA21226.999
KSenseInD21511.285
KSenseShuntA26281.046380952383
KSenseShuntD26633.019523809522
KShuntA1051.368
KShuntD1014.248

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CmlBias0800
CmlBias1400
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux00
DataMergeOutMux11
DataMergeOutMux22
DataMergeOutMux33
SerEnLane1
SldoTrimA7
SldoTrimD9
Parameter
ADCcalPar
  • 11.602
  • 0.182
  • 10000.0
Name0x1548a
ChipId15
InjCap7.780000000000001
NfDSLDO1.2846440826516143
NfASLDO1.2841414776270468
NfACB1.2816571727913266
VcalPar
  • 3.201
  • 0.196
IrefTrim8
KSenseInA21226.999
KSenseInD21511.285
KSenseShuntA26281.046380952383
KSenseShuntD26633.019523809522
KShuntA1051.368
KShuntD1014.248