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20UPGFC0087162 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 64e51b62fc7088729756ae03

This Revision: 64e51b62fc7088729756ae04

Latest Revision: 64e51b62fc7088729756ae04

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	5

Parameter

ADCcalPar	14.912 0.193 10000.0
Name	0x1547a
ChipId	14
InjCap	7.838
NfDSLDO	1.2864511989452139
NfASLDO	1.2853017094228576
NfACB	1.282887781425909
VcalPar	1.89 0.206
IrefTrim	7
KSenseInA	21265.822
KSenseInD	21577.621

KSenseShuntA	26329.112952380954
KSenseShuntD	26715.14980952381
KShuntA	1040.776
KShuntD	1034.391

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	6
SldoTrimD	5

Parameter

ADCcalPar	14.912 0.193 10000.0
Name	0x1547a
ChipId	14
InjCap	7.838
NfDSLDO	1.2864511989452139
NfASLDO	1.2853017094228576
NfACB	1.282887781425909
VcalPar	1.89 0.206
IrefTrim	7
KSenseInA	21265.822
KSenseInD	21577.621
KSenseShuntA	26329.112952380954
KSenseShuntD	26715.14980952381
KShuntA	1040.776
KShuntD	1034.391