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20UPGFC0087178 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: warm

Config: 64e51b5efc7088729756adf5

This Revision: 64e51b5efc7088729756adf6

Latest Revision: 65171cd8242a8062d542eaaa

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2

DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	11.602 0.182 10000.0
Name	0x1548a
ChipId	15
InjCap	7.780000000000001
NfDSLDO	1.2846440826516143
NfASLDO	1.2841414776270468
NfACB	1.2816571727913266
VcalPar	3.201 0.196
IrefTrim	8
KSenseInA	21226.999
KSenseInD	21511.285

KSenseShuntA	26281.046380952383
KSenseShuntD	26633.019523809522
KShuntA	1051.368
KShuntD	1014.248

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	400
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	350
DiffPreampL	550
DiffPreampM	550
DiffPreampR	550
DiffPreampT	550
DiffPreampTL	550
DiffPreampTR	550
DiffVff	60
EnCoreCol0	65535
EnCoreCol1	65535
EnCoreCol2	65535
EnCoreCol3	63
DataMergeOutMux0	0
DataMergeOutMux1	1
DataMergeOutMux2	2
DataMergeOutMux3	3
SerEnLane	1
SldoTrimA	7
SldoTrimD	9

Parameter

ADCcalPar	11.602 0.182 10000.0
Name	0x1548a
ChipId	15
InjCap	7.780000000000001
NfDSLDO	1.2846440826516143
NfASLDO	1.2841414776270468
NfACB	1.2816571727913266
VcalPar	3.201 0.196
IrefTrim	8
KSenseInA	21226.999
KSenseInD	21511.285
KSenseShuntA	26281.046380952383
KSenseShuntD	26633.019523809522
KShuntA	1051.368
KShuntD	1014.248