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20UPGFC0087157 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 646c05ac860c8139aedf82a7

This Revision: 646c05ac860c8139aedf82a8

Latest Revision: 65f21bf2aa59dc167b4d1aee

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	200
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	8
SldoTrimD	4

Parameter

ADCcalPar	12.51 0.193 10000.0
Name	0x15475
ChipId	14
InjCap	7.628
NfDSLDO	1.286082039233688
NfASLDO	1.2854497118518697
NfACB	1.2827766915560024
VcalPar	4.829 0.207
IrefTrim	12
KSenseInA	21239.449
KSenseInD	21665.175

KSenseShuntA	26296.460666666666
KSenseShuntD	26823.55
KShuntA	1060.105
KShuntD	1028.822

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	200
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	8
SldoTrimD	4

Parameter

ADCcalPar	12.51 0.193 10000.0
Name	0x15475
ChipId	14
InjCap	7.628
NfDSLDO	1.286082039233688
NfASLDO	1.2854497118518697
NfACB	1.2827766915560024
VcalPar	4.829 0.207
IrefTrim	12
KSenseInA	21239.449
KSenseInD	21665.175
KSenseShuntA	26296.460666666666
KSenseShuntD	26823.55
KShuntA	1060.105
KShuntD	1028.822