20UPGFC0087125 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 646c05ab860c8139aedf82a3

This Revision: 65f208a2aa59dc167b4d1908

Latest Revision: 65f21becaa59dc167b4d1adc

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp0
DiffPreampL0
DiffPreampM0
DiffPreampR0
DiffPreampT0
DiffPreampTL0
DiffPreampTR0
DiffVff0
EnCoreCol00
EnCoreCol10
EnCoreCol20
EnCoreCol30
DataMergeOutMux02
DataMergeOutMux13
DataMergeOutMux20
DataMergeOutMux31
SerEnLane4
SldoTrimA11
SldoTrimD8

Parameter

ADCcalPar
  • 14.161
  • 0.196
  • 10000.0
Name0x15455
ChipId12
InjCap7.762
NfDSLDO1.2871172130641726
NfASLDO1.2863122167616496
NfACB1.2842134764015007
VcalPar
  • 4.414
  • 0.21
IrefTrim9
KSenseInA21239.202
KSenseInD21669.469
KSenseShuntA26296.154857142858
KSenseShuntD26828.866380952382
KShuntA1063.824
KShuntD1027.158

PixelConfig

Diff from previous revision 65f1df93d29db8ca8129691d

No diff is present.