20UPGFC0087157 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: cold

Config: 646c05a9860c8139aedf829f

This Revision: 646c05a9860c8139aedf82a0

Latest Revision: 646c05a9860c8139aedf82a0

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane8
SldoTrimA8
SldoTrimD4

Parameter

ADCcalPar
  • 12.51
  • 0.193
  • 10000.0
Name0x15475
ChipId14
InjCap7.628
NfDSLDO1.286082039233688
NfASLDO1.2854497118518697
NfACB1.2827766915560024
VcalPar
  • 4.829
  • 0.207
IrefTrim12
KSenseInA21239.449
KSenseInD21665.175
KSenseShuntA26296.460666666666
KSenseShuntD26823.55
KShuntA1060.105
KShuntD1028.822

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane8
SldoTrimA8
SldoTrimD4
Parameter
ADCcalPar
  • 12.51
  • 0.193
  • 10000.0
Name0x15475
ChipId14
InjCap7.628
NfDSLDO1.286082039233688
NfASLDO1.2854497118518697
NfACB1.2827766915560024
VcalPar
  • 4.829
  • 0.207
IrefTrim12
KSenseInA21239.449
KSenseInD21665.175
KSenseShuntA26296.460666666666
KSenseShuntD26823.55
KShuntA1060.105
KShuntD1028.822