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20UPGFC0086627 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: LP

Config: 6466564f6050bd2ad2ac368f

This Revision: 6466564f6050bd2ad2ac3690

Latest Revision: 652f5df898262c9e8e515a6e

Global Config

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	200
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3

DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	13.21 0.181 10000.0
Name	0x15263
ChipId	14
InjCap	8.049
NfDSLDO	1.2858530955734209
NfASLDO	1.2850634888001302
NfACB	1.2835704141742719
VcalPar	4.258 0.195
IrefTrim	13
KSenseInA	21232.637
KSenseInD	21560.576

KSenseShuntA	26288.026761904763
KSenseShuntD	26694.046476190477
KShuntA	1097.019
KShuntD	1059.987

PixelConfig

Diff from previous revision None

RD53B

GlobalConfig

AuroraActiveLanes	1
CmlBias0	800
CmlBias1	200
CmlBias2	0
SerEnTap	1
SerInvTap	1
MonitorEnable	1
MonitorI	63
MonitorV	1
ServiceBlockEn	1
DiffPreComp	0
DiffPreampL	0
DiffPreampM	0
DiffPreampR	0
DiffPreampT	0
DiffPreampTL	0
DiffPreampTR	0
DiffVff	0
EnCoreCol0	0
EnCoreCol1	0
EnCoreCol2	0
EnCoreCol3	0
DataMergeOutMux0	1
DataMergeOutMux1	2
DataMergeOutMux2	3
DataMergeOutMux3	0
SerEnLane	8
SldoTrimA	9
SldoTrimD	6

Parameter

ADCcalPar	13.21 0.181 10000.0
Name	0x15263
ChipId	14
InjCap	8.049
NfDSLDO	1.2858530955734209
NfASLDO	1.2850634888001302
NfACB	1.2835704141742719
VcalPar	4.258 0.195
IrefTrim	13
KSenseInA	21232.637
KSenseInD	21560.576
KSenseShuntA	26288.026761904763
KSenseShuntD	26694.046476190477
KShuntA	1097.019
KShuntD	1059.987