20UPGFC0086627 Chip Configuration

Stage: MODULE/INITIAL_WARM

Branch: cold

Config: 6466564b6050bd2ad2ac3687

This Revision: 6466564b6050bd2ad2ac3688

Latest Revision: 652edb7887c5aa30c3b2ef2f

Global Config

AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane8
SldoTrimA9
SldoTrimD6

Parameter

ADCcalPar
  • 13.21
  • 0.181
  • 10000.0
Name0x15263
ChipId14
InjCap8.049
NfDSLDO1.2858530955734209
NfASLDO1.2850634888001302
NfACB1.2835704141742719
VcalPar
  • 4.258
  • 0.195
IrefTrim13
KSenseInA21232.637
KSenseInD21560.576
KSenseShuntA26288.026761904763
KSenseShuntD26694.046476190477
KShuntA1097.019
KShuntD1059.987

PixelConfig

Diff from previous revision None

RD53B
GlobalConfig
AuroraActiveLanes1
CmlBias0800
CmlBias1200
CmlBias20
SerEnTap1
SerInvTap1
MonitorEnable1
MonitorI63
MonitorV1
ServiceBlockEn1
DiffPreComp350
DiffPreampL550
DiffPreampM550
DiffPreampR550
DiffPreampT550
DiffPreampTL550
DiffPreampTR550
DiffVff60
EnCoreCol065535
EnCoreCol165535
EnCoreCol265535
EnCoreCol363
DataMergeOutMux01
DataMergeOutMux12
DataMergeOutMux23
DataMergeOutMux30
SerEnLane8
SldoTrimA9
SldoTrimD6
Parameter
ADCcalPar
  • 13.21
  • 0.181
  • 10000.0
Name0x15263
ChipId14
InjCap8.049
NfDSLDO1.2858530955734209
NfASLDO1.2850634888001302
NfACB1.2835704141742719
VcalPar
  • 4.258
  • 0.195
IrefTrim13
KSenseInA21232.637
KSenseInD21560.576
KSenseShuntA26288.026761904763
KSenseShuntD26694.046476190477
KShuntA1097.019
KShuntD1059.987