20UPGPQ4610026

OB_LOADED_MODULE_CELL/PIGTAIL_INSERTION

Component Information

Serial Number	20UPGPQ4610026
ProdDB ID	dd3895…241607
LocalDB ID	66a2880cebdf60004362e6f0
Component Type	MODULE_PCB
Parents	20UPGM23610026
Children	No match.
Flags

Damaged during handling

Other issues

Too dirty to be used

Brown marks on traces

Additional cleaning done

Has misplaced pads due to solder mask issue

Used for dummy modules

Used for PCB QA

Properties

Item	Value
PCB Manufacturer	Yamashita Material
PCB design version readonly	4
PCB vendor technology readonly	6
SMD population vendor	Hayashi REPIC Co.

Comments

Test: LAYER_THICKNESS QC Passed

(Stage: PCB_RECEPTION)

Basic View Only: custom view for this TestRun is not prepared.

Metadata

Key	Data
QC Passed	True
Date	a year ago
component ObjectId	66a2880cebdf60004362e6f0
Stage	PCB_RECEPTION
Test Type	LAYER_THICKNESS
Institute ObjectId
User Name	YoichiIkegami
ObjectId of this record	66a350bf6303b43c546a8c9c
ObjectId of RAW record	66a350bf6303b43c546a8c9b
Tags	No tags

Results

Key	Data
ANALYSIS_VERSION	mqat vNone
INSTRUMENT	None
OPERATOR	Takumi Kumayama
BOTTOM_LAYER_THICKNESS	34.7
COVERLAY_WITH_ADHESIVE_THICKNESS	87.2
DIELECTRIC_THICKNESS	83.3
INNER_LAYER_THICKNESS	10.5
THICKNESS	229
TOP_LAYER_THICKNESS	31.4

RAW Results Record

Download RAW

_id

66a350bf6303b43c546a8c9b

raw

serialNumber

testType

subtestType

results

stage

component

dbVersion

address

sys

20UPGPQ4610026

LAYER_THICKNESS

property

OPERATOR	None
INSTRUMENT	None
ANALYSIS_VERSION	None

comment

metadata

QCHELPER_VERSION

4.0.dev1

MODULE_SN

20UPGPQ4610026

Measurement

BOTTOM_LAYER_THICKNESS	34.7
COVERLAY_WITH_ADHESIVE_THICKNESS	87.2
DIELECTRIC_THICKNESS	83.3
INNER_LAYER_THICKNESS	10.5
SOLDERMASK_THICKNESS	19.4
THICKNESS	229.0
TOP_LAYER_THICKNESS	31.4

Metadata

Measurements

TOP_LAYER_THICKNESS

None

INNER_LAYER_THICKNESS

None

BOTTOM_LAYER_THICKNESS

None

DIELECTRIC_THICKNESS

None

COVERLAY_WITH_ADHESIVE_THICKNESS

None

THICKNESS

None

PCB_RECEPTION

66a2880cebdf60004362e6f0

1.01

64657cef8d79bac1f3f0057a

mts	2024-07-26 07:31:11.134000
cts	2024-07-26 07:31:11.134000
rev	0

rawHash

c0d2b27f008b4c87580ab8f260b53094

stage

PCB_RECEPTION

ProductionDB Record

Expand ProductionDB Record

66c42a41dd30980043ee726e

state

ready

stateTs

2024-08-20T05:31:45.294Z

stateUserIdentity

5738-1891-1

date

2024-07-26T07:31:00.000Z

testType

id	63ef3b1919aead0036ceca12
code	LAYER_THICKNESS
name	Layer thickness measurement
state	active

institution

id	5d31879ddf98f200097387f5
code	KEK
name	High Energy Accelerator Research Organization (KEK)

user

id	6344c3dd9aa738001bd1baff
userIdentity	5738-1891-1
firstName	Yoichi
middleName
lastName	Ikegami

runNumber

66a350bf6303b43c546a8c9c

passed

True

problems

False

properties

code	name	dataType	valueType	required	value
ANALYSIS_VERSION	Analysis Version	string	single	False	None
INSTRUMENT	Instrument	string	single	False	None
OPERATOR	Operator	string	single	False	Takumi Kumayama

results

code	name	dataType	valueType	arrayDimensions	additional	value	associateChild
BOTTOM_LAYER_THICKNESS	Bottom layer thickness (including ENIG) [µm]	float	single	None	False	34.7	None
COVERLAY_WITH_ADHESIVE_THICKNESS	Coverlay with Adhesive thickness [µm]	float	single	None	False	87.2	None
DIELECTRIC_THICKNESS	Dielectric thickness [µm]	float	single	None	False	83.3	None
INNER_LAYER_THICKNESS	Inner layer thickness [µm]	float	single	None	False	10.5	None
THICKNESS	Total PCB thickness [µm]	float	single	None	False	229	None
TOP_LAYER_THICKNESS	Top layer thickness (including ENIG) [µm]	float	single	None	False	31.4	None

cts

2024-08-20T05:31:45.294Z

sys

cts	2024-08-20T05:31:45.294Z
mts	2024-10-07T06:45:53.075Z
rev	2

defects

comments

None

attachments

code

dateTime

title

description

contentType

type

binaryStoreg02

filename

user

d929b01b3c38022c21e74651bafea178

2024-08-20T05:31:45.607Z

RAW

application/json

file

True

20UPGPQ4610026_PCB_RECEPTION_LAYER_THICKNESS_66c42a41dd30980043ee726e_66a350bf6303b43c546a8c9b.json

id	6344c3dd9aa738001bd1baff
userIdentity	5738-1891-1
firstName	Yoichi
middleName
lastName	Ikegami

components

code

state

stateTs

stateUserIdentity

dummy

completed

completedTs

completedUserIdentity

trashed

trashedTs

trashedUserIdentity

serialNumber

alternativeIdentifier

project

subproject

componentType

type

properties

testedAtStage

institution

66a2880cebdf60004362e6f0

dd3895cac196616c94017df1f0241607

ready

2024-07-25T17:14:52.959Z

24-779-1

False

None

False

None

20UPGPQ4610026

None

code	P
name	Pixels

code	PG
name	Pixel general

code	PCB
name	Module PCB

code	QUAD_PCB
name	Quad PCB

code PCB_MANUFACTURER
name PCB Manufacturer
dataType string
required True
default False
value Yamashita Material

code

PCB_DESIGN_VERSION

name

PCB design version

dataType

codeTable

required

True

default

False

value

Production OS

codeTable

code	value
0	RD53A
1	Prototype
2	Preproduction OS
3	Preproduction IS
4	Production OS
5	Production IS
9	No chip

code

PCB_VENDOR_TECHNOLOGY

name

PCB vendor technology

dataType

codeTable

required

True

default

False

value

Yamashita Material (75 mum trace)

codeTable

code	value
1	EPEC (100 mum trace)
2	NCAB (100 mum trace)
3	ALTAFLEX (75 mum trace)
4	SFCircuits (100 mum trace)
5	PHOENIX (100 mum trae)
6	Yamashita Material (75 mum trace)
7	NCAB (75 mum trace)
8	Tecnomec (100 mum trace)

code SMD_POPULATION_VENDOR
name SMD population vendor
dataType string
required False
default False
value Hayashi REPIC Co.

code	PCB_RECEPTION
name	Reception
order	0
initial	True
final	False

code	KEK
name	High Energy Accelerator Research Organization (KEK)

Current Stage: Insertion of pigtail and strain relief glueing

No tests are allocated for this stage.

Past QC Stages and Results

Module PCB tab cutting (in Combined Method) (OB_LOADED_MODULE_CELL/TAB_CUTTING)

Reception at Cell Integration Sites (OB_LOADED_MODULE_CELL/RECEPTION)

OB Loaded Module Cell Complete (OB_LOADED_MODULE_CELL/COMPLETE)

OB Loaded Module Cells failed test, needs investigation (OB_LOADED_MODULE_CELL/UNHAPPY)

Grading of OB Loaded Module Cells (OB_LOADED_MODULE_CELL/QC_STATUS)

Envelope Check (OB_LOADED_MODULE_CELL/ENVELOPE_CHECK)

Thermal Conductivity Test at Warm Temperature (OB_LOADED_MODULE_CELL/THERMAL_WARM)

Thermal Conductivity Test at Cold Temperature (OB_LOADED_MODULE_CELL/THERMAL_COLD)

Electrical Tests at Cold Temperature (OB_LOADED_MODULE_CELL/FINAL_COLD)

Electrical Tests at Warm Temperature (OB_LOADED_MODULE_CELL/FINAL_WARM)

Cold Cycle (OB_LOADED_MODULE_CELL/THERMAL_CYCLES)

Module to cell assembly (OB_LOADED_MODULE_CELL/ASSEMBLY)

Initial state to associate bare cell to module (OB_LOADED_MODULE_CELL/INIT)

Electrical testing at reception of LLS (LLS/RECEPTION)

Electrical testing on LLS at cold temperature (LLS/POST_TC_COLD)

Electrical testing on LLS at warm temperature (LLS/POST_TC_WARM)

Electrical testing before thermal cycling on LLS at cold temperature (LLS/PRE_TC_COLD)

Electrical testing before thermal cycling on LLS at warm temperature (LLS/PRE_TC_WARM)

Module PCB tab cutting (MODULE/TAB_CUTTING)

Module reception (MODULE/RECEPTION)

Module Complete (MODULE/COMPLETE)

Modules damaged, impossible to recover (MODULE/GRAVEYARD)

Stage for QA modules and others not to be considered in yield calculation (MODULE/NOTCONSIDEREDINYIELDS)

Modules failed test, needs investigation (MODULE/UNHAPPY)

Ranking of the module (MODULE/QC_STATUS)

Final flatness measurement (MODULE/FINAL_METROLOGY)

Final Cold (MODULE/FINAL_COLD)

Final Warm (MODULE/FINAL_WARM)

Long Term Stability Test (MODULE/LONG_TERM_STABILITY_TEST)

Thermal Cycles (MODULE/THERMAL_CYCLES)

Post-Parylene Cold (MODULE/POST_PARYLENE_COLD)

Post-Parylene Warm (MODULE/POST_PARYLENE_WARM)

Wirebond Protection (alt) (MODULE/WIREBOND_PROTECTION)

Parylene Unmasking (MODULE/PARYLENE_UNMASKING)

Parylene Coating (MODULE/PARYLENE_COATING)

Parylene Masking (MODULE/PARYLENE_MASKING)

Initial Cold (MODULE/INITIAL_COLD)

QC cross-check (module swapping) (MODULE/QC_CROSSCHECK)

Initial Warm (MODULE/INITIAL_WARM)

Wire Bonding (MODULE/WIREBONDING)

Bare module to module PCB assembly (MODULE/ASSEMBLY)

Initial state to associate flex to bare module (MODULE/INIT)

Complete (COMPLETE)

PCB Reception at module site (PCB_RECEPTION_MODULE_SITE)

Test	Local Result	ProdDB Record
Mass (MASS)	No result	N/A
Metrology (METROLOGY)	Registered	Registered
Metrology Triplet Linear (TRIPLET_PCB_LINEAR_METROLOGY)	No result	N/A
Metrology Triplet Ring (TRIPLET_PCB_RING_METROLOGY)	No result	N/A
Visual Inspection (VISUAL_INSPECTION)	No result	N/A

PCB ready for module (PCB_READY_FOR_MODULE)

PCB impossible to recover (PCB/GRAVEYARD)

Test failed, needs investigation (UNHAPPY)

QC (PCB_QC)

Test	Local Result	ProdDB Record
Dowel Tolerance Check (DOWEL_TOLERANCE_CHECK)	No result	N/A
LV and HV Test (HV_LV_TEST)	Registered	Registered

QA post radiation cycle (QA_POST_RADIATION_CYCLE)

Test	Local Result	ProdDB Record
Signal Transmission (SIGNAL_TRANSMISSION)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A

QA post radiation post thermal cycle QC (QA_POST_RADIATION_POST_THERMAL_CYCLE)

Test	Local Result	ProdDB Record
Signal Transmission (SIGNAL_TRANSMISSION)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A

QA pre-radiation cycle (QA_PRE_RADIATION_CYCLE)

Test	Local Result	ProdDB Record
LV and HV Test (HV_LV_TEST)	No result	N/A
Metrology (METROLOGY)	No result	N/A
NTC Verification (NTC_VERIFICATION)	No result	N/A
Signal Transmission (SIGNAL_TRANSMISSION)	No result	N/A
SLDO and precision resistors (SLDO_RESISTORS)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A
Wirebond pull test (WIREBOND_PULL_TEST)	No result	N/A

QA post-thermal cycle / thermal shock (QA_POST_THERMAL_CYCLE)

Test	Local Result	ProdDB Record
LV and HV Test (HV_LV_TEST)	No result	N/A
NTC Verification (NTC_VERIFICATION)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A
Wirebond pull test (WIREBOND_PULL_TEST)	No result	N/A

QA pre-thermal cycle / thermal shock (QA_PRE_THERMAL_CYCLE)

Test	Local Result	ProdDB Record
LV and HV Test (HV_LV_TEST)	No result	N/A
Metrology (METROLOGY)	No result	N/A
NTC Verification (NTC_VERIFICATION)	No result	N/A
Signal Transmission (SIGNAL_TRANSMISSION)	No result	N/A
SLDO and precision resistors (SLDO_RESISTORS)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A
Wirebond pull test (WIREBOND_PULL_TEST)	No result	N/A

Population (PCB_POPULATION)

Test	Local Result	ProdDB Record
Component Position Check (COMPONENT_POSITION_CHECK)	No result	N/A
Visual Inspection (VISUAL_INSPECTION)	Registered	Registered

PCB being populated (PCB_BEING_POPULATED)

Reception (PCB_RECEPTION)

Test	Local Result	ProdDB Record
Dowel Tolerance Check (DOWEL_TOLERANCE_CHECK)	No result	N/A
Image capture test (IMAGE_CAPTURE_TEST)	No result	N/A
Layer thickness measurement (LAYER_THICKNESS)	Registered	Registered
Metrology (METROLOGY)	Registered	Registered
Metrology Triplet Linear (TRIPLET_PCB_LINEAR_METROLOGY)	No result	N/A
Metrology Triplet Ring (TRIPLET_PCB_RING_METROLOGY)	No result	N/A
Via resistance (VIA_RESISTANCE)	No result	N/A
Visual Inspection (VISUAL_INSPECTION)	Registered	Registered

Bare PCB Initial (PCB_INIT)

LocalDB Test ID	Stage	Test Name	Inspector	Measurement Date	Analysis Date	Tags	QC Registration
66a350…6a8c9c	PCB_RECEPTION	LAYER_THICKNESS	YoichiIkegami	N/A	a year ago	No tags	Selected
66c2e8…fd9cd9	PCB_RECEPTION	METROLOGY	YoichiIkegami	N/A	a year ago	No tags	Selected
66a350…6a8c9a	PCB_RECEPTION	VISUAL_INSPECTION	YoichiIkegami	N/A	a year ago	No tags	Selected
66f35a…92d2b9	PCB_RECEPTION_MODULE_SITE	METROLOGY	KojiNakamura	N/A	a year ago	No tags	Selected
66f656…49a8e0	PCB_QC	HV_LV_TEST	KojiNakamura	N/A	a year ago	No tags	Selected
66f35a…92d2b6	PCB_POPULATION	VISUAL_INSPECTION	KojiNakamura	N/A	a year ago	No tags	Selected

Stage	Tests
PCB_INIT
PCB_RECEPTION	Visual Inspection (VISUAL_INSPECTION) Metrology (METROLOGY) Dowel Tolerance Check (DOWEL_TOLERANCE_CHECK) Layer thickness measurement (LAYER_THICKNESS) Image capture test (IMAGE_CAPTURE_TEST) Via resistance (VIA_RESISTANCE) Metrology Triplet Linear (TRIPLET_PCB_LINEAR_METROLOGY) Metrology Triplet Ring (TRIPLET_PCB_RING_METROLOGY)
PCB_BEING_POPULATED
PCB_POPULATION	Visual Inspection (VISUAL_INSPECTION) Component Position Check (COMPONENT_POSITION_CHECK)
QA_PRE_THERMAL_CYCLE	SLDO and precision resistors (SLDO_RESISTORS) NTC Verification (NTC_VERIFICATION) Signal Transmission (SIGNAL_TRANSMISSION) Via resistance (VIA_RESISTANCE) Metrology (METROLOGY) LV and HV Test (HV_LV_TEST) Wirebond pull test (WIREBOND_PULL_TEST)
QA_POST_THERMAL_CYCLE	NTC Verification (NTC_VERIFICATION) Via resistance (VIA_RESISTANCE) LV and HV Test (HV_LV_TEST) Wirebond pull test (WIREBOND_PULL_TEST)
QA_PRE_RADIATION_CYCLE	Signal Transmission (SIGNAL_TRANSMISSION) Via resistance (VIA_RESISTANCE) Metrology (METROLOGY) SLDO and precision resistors (SLDO_RESISTORS) NTC Verification (NTC_VERIFICATION) Wirebond pull test (WIREBOND_PULL_TEST) LV and HV Test (HV_LV_TEST)
QA_POST_RADIATION_POST_THERMAL_CYCLE	Signal Transmission (SIGNAL_TRANSMISSION) Via resistance (VIA_RESISTANCE)
QA_POST_RADIATION_CYCLE	Signal Transmission (SIGNAL_TRANSMISSION) Via resistance (VIA_RESISTANCE)
PCB_QC	LV and HV Test (HV_LV_TEST) Dowel Tolerance Check (DOWEL_TOLERANCE_CHECK) Tab cutting and gross defect inspection (QUICK_TAB_CUTTING_INSPECTION)
UNHAPPY
PCB/GRAVEYARD
PCB_READY_FOR_MODULE
PCB_RECEPTION_MODULE_SITE	Visual Inspection (VISUAL_INSPECTION) Mass (MASS) Metrology (METROLOGY) Metrology Triplet Linear (TRIPLET_PCB_LINEAR_METROLOGY) Metrology Triplet Ring (TRIPLET_PCB_RING_METROLOGY)
COMPLETE
MODULE/INIT
MODULE/ASSEMBLY
MODULE/WIREBONDING
MODULE/INITIAL_WARM
MODULE/QC_CROSSCHECK
MODULE/INITIAL_COLD
MODULE/PARYLENE_MASKING
MODULE/PARYLENE_COATING
MODULE/PARYLENE_UNMASKING
MODULE/WIREBOND_PROTECTION
MODULE/POST_PARYLENE_WARM
MODULE/POST_PARYLENE_COLD
MODULE/THERMAL_CYCLES
MODULE/LONG_TERM_STABILITY_TEST
MODULE/FINAL_WARM
MODULE/FINAL_COLD
MODULE/FINAL_METROLOGY
MODULE/QC_STATUS
MODULE/UNHAPPY
MODULE/NOTCONSIDEREDINYIELDS
MODULE/GRAVEYARD
MODULE/COMPLETE
MODULE/RECEPTION
MODULE/TAB_CUTTING
LLS/PRE_TC_WARM
LLS/PRE_TC_COLD
LLS/POST_TC_WARM
LLS/POST_TC_COLD
LLS/RECEPTION
OB_LOADED_MODULE_CELL/INIT
OB_LOADED_MODULE_CELL/ASSEMBLY
OB_LOADED_MODULE_CELL/THERMAL_CYCLES
OB_LOADED_MODULE_CELL/FINAL_WARM
OB_LOADED_MODULE_CELL/FINAL_COLD
OB_LOADED_MODULE_CELL/THERMAL_COLD
OB_LOADED_MODULE_CELL/THERMAL_WARM
OB_LOADED_MODULE_CELL/ENVELOPE_CHECK
OB_LOADED_MODULE_CELL/QC_STATUS
OB_LOADED_MODULE_CELL/UNHAPPY
OB_LOADED_MODULE_CELL/COMPLETE
OB_LOADED_MODULE_CELL/RECEPTION
OB_LOADED_MODULE_CELL/TAB_CUTTING
OB_LOADED_MODULE_CELL/PIGTAIL_INSERTION

20UPGPQ4610026

OB_LOADED_MODULE_CELL/PIGTAIL_INSERTION

Component Information

Properties

Comments

Test: LAYER_THICKNESS QC Passed

(Stage: PCB_RECEPTION)

Basic View Only: custom view for this TestRun is not prepared.

Metadata

Results

RAW Results Record

ProductionDB Record

Current Stage: Insertion of pigtail and strain relief glueing

Past QC Stages and Results

Module PCB tab cutting (in Combined Method) (OB_LOADED_MODULE_CELL/TAB_CUTTING)

Reception at Cell Integration Sites (OB_LOADED_MODULE_CELL/RECEPTION)

OB Loaded Module Cell Complete (OB_LOADED_MODULE_CELL/COMPLETE)

OB Loaded Module Cells failed test, needs investigation (OB_LOADED_MODULE_CELL/UNHAPPY)

Grading of OB Loaded Module Cells (OB_LOADED_MODULE_CELL/QC_STATUS)

Envelope Check (OB_LOADED_MODULE_CELL/ENVELOPE_CHECK)

Thermal Conductivity Test at Warm Temperature (OB_LOADED_MODULE_CELL/THERMAL_WARM)

Thermal Conductivity Test at Cold Temperature (OB_LOADED_MODULE_CELL/THERMAL_COLD)

Electrical Tests at Cold Temperature (OB_LOADED_MODULE_CELL/FINAL_COLD)

Electrical Tests at Warm Temperature (OB_LOADED_MODULE_CELL/FINAL_WARM)

Cold Cycle (OB_LOADED_MODULE_CELL/THERMAL_CYCLES)

Module to cell assembly (OB_LOADED_MODULE_CELL/ASSEMBLY)

Initial state to associate bare cell to module (OB_LOADED_MODULE_CELL/INIT)

Electrical testing at reception of LLS (LLS/RECEPTION)

Electrical testing on LLS at cold temperature (LLS/POST_TC_COLD)

Electrical testing on LLS at warm temperature (LLS/POST_TC_WARM)

Electrical testing before thermal cycling on LLS at cold temperature (LLS/PRE_TC_COLD)

Electrical testing before thermal cycling on LLS at warm temperature (LLS/PRE_TC_WARM)

Module PCB tab cutting (MODULE/TAB_CUTTING)

Module reception (MODULE/RECEPTION)

Module Complete (MODULE/COMPLETE)

Modules damaged, impossible to recover (MODULE/GRAVEYARD)

Stage for QA modules and others not to be considered in yield calculation (MODULE/NOTCONSIDEREDINYIELDS)

Modules failed test, needs investigation (MODULE/UNHAPPY)

Ranking of the module (MODULE/QC_STATUS)

Final flatness measurement (MODULE/FINAL_METROLOGY)

Final Cold (MODULE/FINAL_COLD)

Final Warm (MODULE/FINAL_WARM)

Long Term Stability Test (MODULE/LONG_TERM_STABILITY_TEST)

Thermal Cycles (MODULE/THERMAL_CYCLES)

Post-Parylene Cold (MODULE/POST_PARYLENE_COLD)

Post-Parylene Warm (MODULE/POST_PARYLENE_WARM)

Wirebond Protection (alt) (MODULE/WIREBOND_PROTECTION)

Parylene Unmasking (MODULE/PARYLENE_UNMASKING)

Parylene Coating (MODULE/PARYLENE_COATING)

Parylene Masking (MODULE/PARYLENE_MASKING)

Initial Cold (MODULE/INITIAL_COLD)

QC cross-check (module swapping) (MODULE/QC_CROSSCHECK)

Initial Warm (MODULE/INITIAL_WARM)

Wire Bonding (MODULE/WIREBONDING)

Bare module to module PCB assembly (MODULE/ASSEMBLY)

Initial state to associate flex to bare module (MODULE/INIT)

Complete (COMPLETE)

PCB Reception at module site (PCB_RECEPTION_MODULE_SITE)

PCB ready for module (PCB_READY_FOR_MODULE)

PCB impossible to recover (PCB/GRAVEYARD)

Test failed, needs investigation (UNHAPPY)

QC (PCB_QC)

QA post radiation cycle (QA_POST_RADIATION_CYCLE)

QA post radiation post thermal cycle QC (QA_POST_RADIATION_POST_THERMAL_CYCLE)

QA pre-radiation cycle (QA_PRE_RADIATION_CYCLE)

QA post-thermal cycle / thermal shock (QA_POST_THERMAL_CYCLE)

QA pre-thermal cycle / thermal shock (QA_PRE_THERMAL_CYCLE)

Population (PCB_POPULATION)

PCB being populated (PCB_BEING_POPULATED)

Reception (PCB_RECEPTION)

Bare PCB Initial (PCB_INIT)

All Registered QC Tests

Check QC Flow

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